/**

This file is part of MaCI/GIMnet.

MaCI/GIMnet is free software: you can redistribute it and/or modify it 
under the terms of the GNU Lesser General Public License as published 
by the Free Software Foundation, either version 3 of the License, or 
(at your option) any later version.

MaCI/GIMnet is distributed in the hope that it will be useful, but WITHOUT 
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General Public 
License for more details.

You should have received a copy of the GNU Lesser General Public 
License along with GIMnet. (See COPYING.LESSER) If not, see 
<http://www.gnu.org/licenses/>.

**/
/*******************************************************************************
    FILE NAME:		i82527.h

    PROJECT:		Linux ECAN527/1000 driver, library, and sample programs

    FILE DESCRIPTION:	This header file contains Intel 82527 CAN controller
			chip definitions.

    Copyright (c) 2004 RTD Embedded Technologies, Inc.

    For driver version, compiler, and target information, please refer to the
    file README.TXT.
*******************************************************************************/

#ifndef  _ECAN_I82527_H
# define _ECAN_I82527_H


enum	/* register adrress mapping */
{	/* RO - Read Only, WO - Write Only, RW - Read/Write (default) */

    I82527_CONTROL		= 0x00,
	I82527_CONTROL_CCE		= 0x40,
	I82527_CONTROL_ZERO_MASK	= 0x30,	/* RO */
	I82527_CONTROL_EIE		= 0x08,
	I82527_CONTROL_SIE		= 0x04,
	I82527_CONTROL_IE		= 0x02,
	I82527_CONTROL_INIT		= 0x01,

    I82527_STATUS		= 0x01,
	I82527_STATUS_BUSOFF		= 0x80, /* RO */
	    I82527_STATUS_BUSOFF_SHIFT		= 7,
	I82527_STATUS_ERRWARN		= 0x40, /* RO */
	    I82527_STATUS_ERRWARN_SHIFT		= 6,
	I82527_STATUS_WAKEUP		= 0x20, /* RO */
	    I82527_STATUS_WAKEUP_SHIFT		= 5,
	I82527_STATUS_RXOK		= 0x10,
	    I82527_STATUS_RXOK_SHIFT		= 4,
	I82527_STATUS_TXOK		= 0x08,
	    I82527_STATUS_TXOK_SHIFT		= 3,
	I82527_STATUS_LEC		= 0x07,
	    I82527_STATUS_LEC_NONE		= 0,
	    I82527_STATUS_LEC_STUFF		= 1,
	    I82527_STATUS_LEC_FORM		= 2,
	    I82527_STATUS_LEC_ACK		= 3,
	    I82527_STATUS_LEC_BIT1		= 4,
	    I82527_STATUS_LEC_BIT0		= 5,
	    I82527_STATUS_LEC_CRC		= 6,
	    I82527_STATUS_LEC_CHECK_UPD		= 7, /* WO */

    I82527_CPU_IFACE		= 0x02,
	I82527_CPU_IFACE_HW_RESET	= 0x80, /* RO */
	I82527_CPU_IFACE_DSC		= 0x40,
	I82527_CPU_IFACE_DMC		= 0x20,
	I82527_CPU_IFACE_PWD		= 0x10,
	I82527_CPU_IFACE_SLEEP		= 0x08,
	I82527_CPU_IFACE_MUX		= 0x04,
	I82527_CPU_IFACE_CEN		= 0x01,

    I82527_RESERVED_03		= 0x03,

    I82527_HIGH_SPEED_READ_0	= 0x04,
    I82527_HIGH_SPEED_READ_1	= 0x05,

    I82527_GLOBAL_MASK_STD_BASE	= 0x06,
	I82527_GLOBAL_MASK_STD_LEN	= 2,
	I82527_GLOBAL_MASK_STD1_ONEMASK	= 0x1F, /* always 1 */

    I82527_GLOBAL_MASK_EXT_BASE	= 0x08,
	I82527_GLOBAL_MASK_EXT_LEN	= 4,
	I82527_GLOBAL_MASK_EXT3_ZEROMASK = 0x07, /* always 0 */

    I82527_MSG15_MASK_BASE		= 0x0C,
	I82527_MSG15_MASK_LEN		= 4,
	I82527_MSG15_MASK_3_ZEROMASK	= 0x07, /* always 0 */

    I82527_CLKOUT		= 0x1F,
	I82527_CLKOUT_ZEROMASK		= 0xC0,
	I82527_CLKOUT_SL		= 0x30,
	    I82527_CLKOUT_SL_GT24		= 0x00, /*      CLKOUT >  24 */
	    I82527_CLKOUT_SL_GT16_LE24		= 0x10, /* 16 < CLKOUT <= 24 */
	    I82527_CLKOUT_SL_GT08_LE16		= 0x20, /*  8 < CLKOUT <= 16 */
	    I82527_CLKOUT_SL_LT08		= 0x30, /*      CLKOUT <   8 */
	I82527_CLKOUT_CDV		= 0x0F,
	    I82527_CLKOUT_CDV_1			= 0x00,
	    I82527_CLKOUT_CDV_2			= 0x01,
	    I82527_CLKOUT_CDV_3			= 0x02,
	    I82527_CLKOUT_CDV_4			= 0x03,
	    I82527_CLKOUT_CDV_5			= 0x04,
	    I82527_CLKOUT_CDV_6			= 0x05,
	    I82527_CLKOUT_CDV_7			= 0x06,
	    I82527_CLKOUT_CDV_8			= 0x07,
	    I82527_CLKOUT_CDV_9			= 0x08,
	    I82527_CLKOUT_CDV_10		= 0x09,
	    I82527_CLKOUT_CDV_11		= 0x0A,
	    I82527_CLKOUT_CDV_12		= 0x0B,
	    I82527_CLKOUT_CDV_13		= 0x0C,
	    I82527_CLKOUT_CDV_14		= 0x0D,
	    I82527_CLKOUT_CDV_15		= 0x0E,
	    I82527_CLKOUT_CDV_RSRV		= 0x0F,

    I82527_BUS_CONFIG		= 0x2F,
	I82527_BUS_CONFIG_COBY		= 0x40,
	I82527_BUS_CONFIG_POL		= 0x20,
	I82527_BUS_CONFIG_DCT1		= 0x08,
	I82527_BUS_CONFIG_DCR1		= 0x02,
	I82527_BUS_CONFIG_DCR0		= 0x01,

    I82527_BIT_TIMING_0		= 0x3F,
	I82527_BIT_TIMING_0_SJW		= 0xC0,
	    I82527_BIT_TIMING_0_SJW_SHIFT	= 6,
	I82527_BIT_TIMING_0_BRP		= 0x3F,

    I82527_BIT_TIMING_1		= 0x4F,
	I82527_BIT_TIMING_1_SPL		= 0x80,
	I82527_BIT_TIMING_1_TSEG2	= 0x70,
	    I82527_BIT_TIMING_1_TSEG2_SHIFT	= 4,
	I82527_BIT_TIMING_1_TSEG1	= 0x0F,

    I82527_INT_ID		= 0x5F,

    I82527_RESERVED_6F		= 0x6F,
    I82527_RESERVED_7F		= 0x7F,
    I82527_RESERVED_8F		= 0x8F,

    I82527_P1_CONF		= 0x9F,	/* 0's - input, 1's - output */
    I82527_P2_CONF		= 0xAF,	/* 0's - input, 1's - output */
    I82527_P1_IN		= 0xBF,
    I82527_P2_IN		= 0xCF,
    I82527_P1_OUT		= 0xDF,
    I82527_P2_OUT		= 0xEF,
    I82527_SERIAL_RESET		= 0xFF,	/* synchronization */

    I82527_MSG_NR_FIRST		= 1,
    I82527_MSG_NR_LAST		= 15,

    /* from 0, first message is 1 */
    I82527_MSG_STEP		= 0x10, /* increment of msg addr */
    I82527_MSG_SIZE		= 0x0F,

	I82527_MSG_CONTROL0		= 0,

	    I82527_MSG_CONTROL0_VALID_MASK	= 0xC0,
	    I82527_MSG_CONTROL0_VALID_0		= 0x40,
	    I82527_MSG_CONTROL0_VALID_1		= 0x80,
	    I82527_MSG_CONTROL0_VALID_NOCHANGE	= 0xC0,

	    I82527_MSG_CONTROL0_TXIE_MASK	= 0x30,
	    I82527_MSG_CONTROL0_TXIE_0		= 0x10,
	    I82527_MSG_CONTROL0_TXIE_1		= 0x20,
	    I82527_MSG_CONTROL0_TXIE_NOCHANGE	= 0x30,

	    I82527_MSG_CONTROL0_RXIE_MASK	= 0x0C,
	    I82527_MSG_CONTROL0_RXIE_0		= 0x04,
	    I82527_MSG_CONTROL0_RXIE_1		= 0x08,
	    I82527_MSG_CONTROL0_RXIE_NOCHANGE	= 0x0C,

	    I82527_MSG_CONTROL0_INT_PND_MASK	= 0x03,
	    I82527_MSG_CONTROL0_INT_PND_0	= 0x01,
	    I82527_MSG_CONTROL0_INT_PND_1	= 0x02,
	    I82527_MSG_CONTROL0_INT_PND_NOCHANGE= 0x03,

	    I82527_MSG_CONTROL0_MSGVAL_INVALIDATE = 0x7F,

	I82527_MSG_CONTROL1		= 1,

	    I82527_MSG_CONTROL1_RMT_PND_MASK	= 0xC0, /* RO */
	    I82527_MSG_CONTROL1_RMT_PND_0	= 0x40, /* RO */
	    I82527_MSG_CONTROL1_RMT_PND_1	= 0x80, /* RO */
	    I82527_MSG_CONTROL1_RMT_PND_NOCHANGE= 0xC0, /* RO */

	    I82527_MSG_CONTROL1_TXREQ_MASK	= 0x30,
	    I82527_MSG_CONTROL1_TXREQ_0		= 0x10,
	    I82527_MSG_CONTROL1_TXREQ_1		= 0x20,
	    I82527_MSG_CONTROL1_TXREQ_NOCHANGE	= 0x30,

	    /* for receive direction */
	    I82527_MSG_CONTROL1_LOST_MASK	= 0x0C,
	    I82527_MSG_CONTROL1_LOST_0		= 0x04,
	    I82527_MSG_CONTROL1_LOST_1		= 0x08,
	    I82527_MSG_CONTROL1_LOST_NOCHANGE	= 0x0C,

	    /* for transmit direction */
	    I82527_MSG_CONTROL1_CPU_UPD_MASK	= 0x0C,
	    I82527_MSG_CONTROL1_CPU_UPD_0	= 0x04,
	    I82527_MSG_CONTROL1_CPU_UPD_1	= 0x08,
	    I82527_MSG_CONTROL1_CPU_UPD_NOCHANGE= 0x0C,

	    I82527_MSG_CONTROL1_NEWDAT_MASK	= 0x03,
	    I82527_MSG_CONTROL1_NEWDAT_0	= 0x01,
	    I82527_MSG_CONTROL1_NEWDAT_1	= 0x02,
	    I82527_MSG_CONTROL1_NEWDAT_NOCHANGE	= 0x03,

	I82527_MSG_ID_BASE		= 2,
	    I82527_MSG_ID_LEN			= 4,
	    I82527_MSG_ID_LEN_EXT		= 4,
	    I82527_MSG_ID_LEN_STD		= 2,
	    I82527_MSG_ID_3_ZEROMASK		= 0x07, /* RO, always 0 */

	I82527_MSG_CONF		= 6,

	    I82527_MSG_CONF_DLC		= 0xF0,
	    I82527_MSG_CONF_DLC_SHIFT	= 4,

	    I82527_MSG_CONF_DIR_TX	= 0x08,

	    I82527_MSG_CONF_EXTID	= 0x04,

	    I82527_MSG_CONF_ZEROMASK	= 0x03, /* RO, always 0 */

	I82527_MSG_DATA_BASE	= 7,
	I82527_MSG_DATA_LEN	= 8,


    I82527_RAM_SIZE	= 0x100
};


#endif	/* _ECAN_I82527_H */
